Sr. Manager Silicon Design Engineering ( Sr. PD Manager )

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, we are dedicated to transforming lives with groundbreaking technology, enriching industries, communities, and the world. Our mission is to design and deliver exceptional products that power next-generation computing experiences—spanning data centers, artificial intelligence, PCs, gaming, and embedded systems. This mission is underpinned by AMD’s culture of pushing the limits of innovation, solving critical challenges, and fostering collaboration, humility, and inclusivity.

Together, AMD advances the future.

Position: Senior Manager – Silicon Design Engineer

Role Overview:

As a Senior Physical Design (PD) Manager, you will lead the implementation and execution of physical design for next-generation SOCs. This role involves managing a PD team responsible for end-to-end execution from RTL to GDSII. You will collaborate with SOC architects, physical design leads, and IP teams to ensure first-pass silicon success, leveraging cutting-edge process technologies to deliver industry-leading designs.

The Ideal Candidate:

You are a seasoned leader in physical design with a track record of managing successful SOC tape-outs. With a deep understanding of PnR implementation and backend convergence activities, you are detail-oriented, self-driven, and thrive in managing cross-functional teams. Strong communication and presentation skills are essential, along with the ability to inspire and guide a team of engineers towards project success.

Key Responsibilities:

• Leadership & Management:

  • Lead a physical design team to implement and converge complex multi-million gate tiles, subchips, and full-chip SOC designs.
  • Drive end-to-end physical design execution, from RTL to GDSII, including signoff and physical verification.
  • Manage team goals, performance evaluations, and career development plans.

• Technical Execution:

  • Deliver high-quality GDS outputs, ensuring all design milestones and project timelines are met.
  • Oversee horizontal signoff flows, including VCLP, formal equivalence, low power checks, timing convergence (tile-level and FCT), and full-chip integration flows.
  • Collaborate with CAD and EDA vendors to enhance physical design methodologies and ensure robust PPA.

• Cross-Functional Collaboration:

  • Work with cross-functional teams across different geographies to drive continuous improvements and solve design challenges.
  • Provide technical guidance, direction, and support to the engineering team.

• Project Tracking:

  • Monitor design convergence status and milestones across all phases of the design cycle.
  • Ensure thorough documentation and effective communication of project progress to stakeholders.

Preferred Experience:

• 15+ years of industry experience in physical design, managing successful tape-outs across RTL to GDSII.
• Expertise in block-level implementation, including floorplanning, timing closure, and physical verification.
• Hands-on experience with physical design verification techniques such as:
  • Formal equivalence, IR&EM, timing closure (STA), physical verification, VSI, and low-power checks.
• Proficiency with industry-standard EDA tools, such as Fusion Compiler, ICC2, PrimeTime, RedHawk, and PTPX.
• Exceptional presentation, communication, and interpersonal skills.

Qualifications:

• B.Tech/M.Tech/MS/Ph.D. in Computer Engineering, Electronics, or Electrical Engineering.
• Proven experience in leading and managing SOC projects with at least two successful tape-outs.
• Strong background in physical design methodologies for advanced process nodes.