Full Chip Floorplan Engineer

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, we are dedicated to transforming lives with innovative technology that enriches industries, communities, and the world. Our mission is to design cutting-edge products that drive next-generation computing experiences—powering data centers, artificial intelligence, PCs, gaming, and embedded systems. At the heart of this mission is AMD’s culture, built on pushing the boundaries of innovation, solving critical challenges, and embracing collaboration, humility, and inclusivity.

Together, AMD advances the future.

Position: MTS Silicon Design Engineer – Full Chip FloorPlan (FCFP)

Role Overview:

AMD seeks an experienced SOC Full Chip FloorPlan (FCFP) Engineer to contribute to the development of next-generation graphics designs. As part of the RTG SOC team, you will be responsible for implementing and managing critical activities in Graphics SOCs. This involves everything from setting up workspaces and coordinating block interactions in a System-on-Chip environment to addressing performance, power, and area (PPA) optimization and automating workflows for efficient processes. The role demands innovation, technical expertise, and a proactive approach to overcoming new challenges.

The Ideal Candidate:

You are passionate about modern, complex processor design and implementation. A collaborative team player with strong analytical and problem-solving skills, you excel in communication and thrive in a fast-paced, multi-site working environment.

Key Responsibilities:

• Lead Full Chip Floorplan tasks for advanced technologies (5nm and below).
• Work on physical design projects involving high-frequency (GHz range) and cutting-edge technologies.
• Understand architecture constraints, project schedules, task volumes, and resource requirements from a physical design perspective.
• Plan and execute tasks, estimating area and time requirements, delegating work, and meeting milestones across multiple projects.
• Perform all aspects of physical design, including:
  • Floorplanning, placement, clock-tree synthesis (CTS), routing, cross-talk and noise reduction, extraction, IR drop, IO pad-ring design, and LVS/DRC checks.
• Execute Full Chip PNR (Place and Route), partitioning, and bump placement.
• Drive low-power and high-performance design implementation.
• Debug and optimize workflows; enhance automation for improved efficiency.
• Collaborate with cross-functional and cross-site teams, maintaining seamless communication.
• Utilize expertise in tools such as Cadence Encounter, Synopsys ICC, and Cadence Innovus to execute designs.
• Support the design and integration of critical analog, mixed-signal, and custom digital blocks at the full-chip level.
• Apply analog layout principles, including matching, electro-migration, latch-up, coupling, IR-drop, and parasitic device management.
• Contribute to multiple successful tape-outs, leveraging extensive experience and advanced methodologies.

Preferred Experience:

• 9+ years of experience in floorplanning, physical design, or related fields.
• Deep understanding of sub-5nm designs and physical design processes.
• Strong problem-solving skills, with the ability to debug and address floorplanning challenges.
• Proficiency in scripting for enhanced efficiency in floorplanning workflows.
• Familiarity with custom 3DIC designs (a plus).
• Demonstrated ability to work effectively in cross-functional, multi-site teams across time zones.
• Creative thinker capable of “out-of-the-box” solutions.

Academic Qualifications:

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.