DFT – Sr. Design Engineer 1

Job Posted On

10-10-2024 

Company Group

Tessolve Semiconductor Private Limited

Department

Digital Design 1

Employee Type

Regular Employee-Probation (IN)

Designation

Sr. Design Engineer 1

Location

  • Noida, Uttar Pradesh, India (TESIN-ND)
  • Electronic City, Bengaluru, Karnataka, India (TESIN-EC)
  • Guindy, Chennai, Tamil Nadu, India (TESIN-GCH)
  • Jubilee Hills, Hyderabad, Telangana, India (TESIN-HYD)
  • ORR, Bengaluru, Karnataka, India (TESIN-ORR)
  • Sarjapur Road, Bengaluru, Karnataka, India (TESIN-SJP)

Experience Required

4 – 6 years

Job Summary

Position: Sr. Design Engineer 1

Experience: 4+ relevant experience.

Location –  India

Education: B.Tech/M.Tech

To be successful in this role you will:

Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design  for Test  skills  and Tools .

Technical Skillset Required:

  • Good knowledge in DFT Skills
  • Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation & GLS .
  • Prior experience in Synsopsys or Cadence or Mentor tools Like Tetramax, Modus ,Tessent  and DC tools
  • Hands on in MBIST insertion and simulation
  • Knowledge on JTAG is an added advantage .
  • Good Simulation debugging skills
  • Technical Documentation: uArchitecture Specification, SoC Integration Specification
  • Good exposure to Scripting skills like Perl or Python or Shell or TCL .

Don’t miss out, CLICK HERE (to apply before the link expires)