- Category: EngineeringHire Type: EmployeeJob ID 6788
What You’ll Need:
- MSc with 2 years of experience in IC design.
- Familiarity with transistor-level circuit design and CMOS design fundamentals.
- In-depth knowledge of setup and hold timing analysis.
- Detailed experience in timing characterization, modeling, simulation, and verification.
- Familiarity with custom digital design (i.e., high-speed logic paths).
- Experience with tools for timing analysis, such as Primetime, Nanotime, or equivalent.
- Hands-on experience with the physical layout of high-speed circuits is a plus.
- Knowledge of SPICE simulators and simulation methods.
- Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.
- Good communication and documentation skills.
- Accustomed to working in a cross-functional, globally diverse environment at all levels of an organization.
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a highly motivated engineer with both theoretical knowledge and practical experience in analog and mixed-signal integrated circuit design. You thrive in a collaborative environment and enjoy working with a cross-functional team of designers from diverse backgrounds. You are detail-oriented and possess strong problem-solving skills, which enable you to tackle complex design challenges effectively. Your excellent communication and documentation skills help you convey technical information clearly and concisely. You are familiar with the latest FinFET CMOS processes and have hands-on experience with IC design tools and methodologies. Your background in transistor-level circuit design and CMOS fundamentals makes you a valuable asset to our team. You are proactive, adaptable, and always eager to learn and grow in a fast-paced, innovative environment.
What You’ll Be Doing:
- Directing and guiding the activities of a team of engineers characterizing timing, analyzing timing results, and generating timing models of high-speed SERDES IP.
- Developing and aligning timing flow and methodology to ensure efficiency and quality of the team’s deliverables.
- Conducting design reviews and evaluating final results of timing views and reports.
- Presenting results of timing assessments or critical issue investigations and making recommendations for actions necessary to achieve desired results.
- Ensuring the team follows processes for maximum design quality.
- Consulting on the timing characteristics of the SerDes IP product and proposing solutions for STA timing closure.
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