ASIC Digital Design Engr, Sr Staff

Job ID 4715

Preferred Qualifications

• Bachelor’s or Master’s degree in relevant field
• 8 to 12 years of relevant experience in micro-architecture, digital design and RTL coding.
• Must have strong Digital Design fundamentals
• Extensive practical hands-on experience in defining micro-architecture and RTL Coding for IP blocks
• Working knowledge and experience on high-speed interface protocols (PCIe/Ethernet) is highly desirable.
• Knowledge in Verilog/VHDL coding, Spyglass LINT/CDC/RDC checks and waiver creation.
• Knowledge in Synthesis, STA, Formal checking, etc.
• Knowledge in Verification and debugging issues.
• Understanding of RTL to GDS flow.
• Familiarity with scripting languages such as Shell/Perl etc. is highly desirable. 

Key Responsibilities

• Understanding IP Specifications
• Defines and develop micro-architecture
• RTL Design using Verilog/System Verilog
• Interacting with cross functional teams to resolve the issues in creative way
• Helping verification team to debug the issue
• Running ASIC development tools including Lint and CDC
• Guides junior peers with aspects of their job