SMTS Silicon Design Engineer

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, we are committed to transforming lives with our innovative technology that enriches industries, communities, and the world. Our mission is to design and deliver exceptional products that drive next-generation computing experiences—spanning data centers, artificial intelligence, PCs, gaming, and embedded systems. At the heart of our mission is a culture of innovation, collaboration, and excellence, fostering diverse perspectives and continuous learning.

Together, AMD advances the future.

Position: SMTS – VC_LP

Role Overview:

As a key member of the VSI-LP (VC_LP) team, you will lead and drive various types of VC_LP checks across different design stages, such as UPF, functional, and structural stages. You will collaborate closely with cross-functional teams, including Physical Design (PD), Front-End Design, and DFT, to ensure VC_LP signoff closure for successful tape-outs. This role requires expertise in power-aware formality checks and the ability to lead schedules while supporting engineering efforts across multiple domains.

Key Responsibilities:

• Perform and manage VC_LP checks at various stages of the chip design cycle, including UPF, functional, and structural.
• Collaborate with implementation teams (PD, Front-End, and DFT) to drive VC_LP signoff closure for tape-out.
• Debug and resolve UPF and implementation issues throughout the design process, from synthesis to GDSII.
• Ensure thorough signoff of power-aware formality checks and low-power flows.
• Plan and execute VC_LP closure across multiple projects, addressing issues and optimizing processes.
• Mentor and lead teams in UPF and VC_LP closure strategies.
• Enhance and debug flow-related issues through scripting and automation.
• Work with industry-standard tools to perform physical design tasks and optimize low-power designs.

Required Skills & Experience:

• Experience:

  • 9+ years of experience in physical design, with a focus on PnR (APR), MV design implementation, and VC_LP signoff checks.
  • Proven track record of successful SOC tape-outs in sub-14nm technology nodes.

• Technical Expertise:

  • Strong knowledge and debugging skills in VC_LP (VSI-LP), power-aware formality, and low-power flows.
  • Expertise in UPF (Unified Power Format) and low-power techniques, with the ability to resolve UPF and implementation challenges.
  • Hands-on experience with low-power design and physical implementation strategies.

• Tools and Processes:

  • Proficiency in tools like Synopsys ICC2, Fusion Compiler, VC_LP, and formal verification tools.
  • Familiarity with all aspects of ASIC physical design, from synthesis to GDSII, is a plus.

• Scripting Skills:

  • Strong scripting abilities to debug issues and enhance workflows.

• Leadership:

  • Experience in leading and mentoring teams in UPF and VC_LP closure processes.

Preferred Qualifications:

• Demonstrated success in managing multiple projects with VC_LP closure and low-power design implementation.
• Experience in advanced technology nodes and physical design signoff methodologies.
• Strong analytical and problem-solving skills, with the ability to work effectively in a fast-paced environment.